Silicon Labs /Series1 /EFR32FG1V /EFR32FG1V131F32GM48 /MSC /READCTRL

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Interpret as READCTRL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (IFCDIS)IFCDIS 0 (AIDIS)AIDIS 0 (ICCDIS)ICCDIS 0 (PREFETCH)PREFETCH 0 (USEHPROT)USEHPROT 0 (WS0)MODE 0 (SCBTP)SCBTP

MODE=WS0

Description

Read Control Register

Fields

IFCDIS

Internal Flash Cache Disable

AIDIS

Automatic Invalidate Disable

ICCDIS

Interrupt Context Cache Disable

PREFETCH

Prefetch Mode

USEHPROT

AHB_HPROT Mode

MODE

Read Mode

0 (WS0): Zero wait-states inserted in fetch or read transfers

1 (WS1): One wait-state inserted for each fetch or read transfer. See Flash Wait-States table for details

SCBTP

Suppress Conditional Branch Target Perfetch

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